I thought one of the major reasons for getting into chiplets was yields and that the I/O die didnt benefit from scaling it down any more?
I don’t think it’s that it doesn’t benefit, but its benefits have little effect on performance. On Zen 4 the io die adds a constant 30W to the power usage (which is a huge portion of the total TDP) so maybe they want want to reclaim some of that
AMD is rumored to be building its next-generation CCD (core complex die) that implements the “Zen 6” microarchitecture, on the 3 nm TSMC N3E foundry node.
I am surprised they are going twith TSMC N3E. One would think they would target one of the 2nm nodes. Or perhaps Zen 6 is coming to marketing in the next Either Zen 6 ~12 years?
3nm came out last year, if 2 comes out this, after a year of apple hogging all the supply it will trickle down to Qualcomm+nvidia next year and everybody else in
20262027. That’s how it seems to go with new nodes.
